This disclosure relates to analog to digital converters, in particular, to FLASH analog to digital converters having a wide input range.
FIG. 1 shows an example of a conventional “FLASH” or “direct conversion” analog to digital converter (ADC). The circuit employs a set of resistors 1 arranged in a chain between a reference voltage 3 and ground (or another reference voltage) to generate a series of voltages at the nodes 5 between the resistors. Typically the resistors all have the same resistance and the variation in voltage from one node to the next is a linear progression. A set of comparators 4 compares the voltage at each of the nodes to the input voltage 2: if the input voltage is higher than the node voltage at a comparator that comparator will saturate and output a ‘1’, otherwise the comparator output will stay low. The comparators will therefore produce a sequence of ‘1’s and ‘0’s at the binary encoder 6 for a given input voltage, with the input voltage level being digitally represented by the point in the sequence at which the switch to ‘0’s. In this manner the input voltage may be digitally sampled to an accuracy determined by the number of comparators (and hence bits).
Such a circuit design suffers from several problems. The accuracy of the ADC is highly dependent on the accuracy and stability of the reference voltage(s) and on the precision of the resistors. Furthermore, the design is susceptible to systematic offset effects in the comparators since all the comparators compare the input voltage to a node voltage dependent on the common reference voltage.
FIG. 2 shows a FLASH ADC having differential inputs. The circuit uses two chains of resistors 20, 29 to generate a series of voltages above the inputs 25, 31 at nodes 22, 32. A pair of current sources 24, 27 connected between voltage rail 28 and the two resistor chains define the voltage at the upper ends of the resistor chains. The comparators 33 are arranged such that the first comparator takes its first input from the first node in the first chain and its second input from the last node in the second chain, the second comparator takes its first input from the second node in the first chain and its second input from the penultimate node in the second chain, and so on, up to the last comparator, which takes its first input from the last node in the first chain and its second input from the first node in the second chain.
When the input voltages 25 and 31 are zero, the voltages at nodes 23 and 30 are equal and the output of comparator 26 is low. When input voltage 25 increases slightly relative to input voltage 31, the voltage at node 23 is higher than that the voltage at node 30 and the output of comparator 26 goes high. When the difference between input voltages 25 and 31 increases by the resolution of the ADC, the output of the next comparator in the series (i.e. one closer to the voltage inputs as shown in FIG. 2) will go high due to the voltage at its first input node being slightly higher than the voltage at its second input node. In this manner the input voltage may be encoded as a binary string, with the input voltage level being digitally represented by the point in the sequence at which the ‘1’s switch to ‘0’s. The binary string is typically encoded by a binary encoder to minimize the amount of redundant information. Thus, an ADC having 64 comparators will output a string of 6 bits. The number of bits is representative of the accuracy of the ADC.
FIG. 3 illustrates the input range of the ADC shown in FIG. 2. The input range is approximately half of the rail-to-rail voltage available to the ADC. This is because it is only possible for half of the comparators (those below comparator 26 in FIG. 2) to be at or close to their thresholds—and therefore relevant to the analog-to-digital conversion—when input voltage 25 is higher than input voltage 31. The other half are relevant when input voltage 25 is lower than input voltage 31.
The input voltage range is restricted by the fact that a constant current flows through the chain of resistors 20 and therefore the voltage dropped across the total length of the resistor chain is fixed. The highest input voltage that can be measured is less than the rail voltage 28 minus the total voltage dropped across the resistor chain. For optimum operation, the total voltage dropped across the resistor chain is set to be approximately half the available rail voltage. Thus at the highest measurable input voltage, the voltage at node 34 is slightly lower than the input voltage 25 and the output of the final comparator 19 in the series goes high.
The input range 36 is further limited by the fact that the current sources typically require a minimum voltage 38 across them in order to maintain the current at its predetermined level. Thus, there is a maximum voltage allowed at the output of the current source before the MOSFET (or other suitable transistor) controlling the current is driven into linear mode and the current (and hence the converter) will no longer be accurate. This voltage is VDD−EP, where EP is the drain-source voltage 38 required to keep the current source saturated and VDD is the rail voltage 35. At the bottom end, the input voltage is limited by how low the driving amplifier can pull the input voltage. Typically the driving amplifier cannot pull the input all the way down to ground. The minimum input voltage is designated by EN, 39 in FIG. 3. The input range of the ADC shown in FIG. 2 is therefore at most 0.5*(VDD−EP−EN).
The circles 37 in FIG. 3 represent the crossover points at the threshold of each bit value, i.e. each point corresponds to the voltage at which the output of a given comparator switches from low to high or vice versa. Note that the threshold voltage is the same for all the comparators.
The desire to reduce operating temperatures and increase the speed of digital electronics is pushing down the operating voltages of digital electronics. It is therefore becoming more important to make the most efficient use of the available voltage range in devices such as analog-to-digital converters. At lower voltage levels, the noise introduced by electronic components becomes more significant and, without careful design, lower tolerances are required of component values which generally increases the area of silicon required. There is therefore a need for an ADC having a large input voltage range (ideally rail-to-rail) and a high tolerance to internal offset voltages.